EPM7384AE芯片解密

EPM7384AE芯片解密最新解密特点:
    8bit turbo 80C52 architecture
　　- 4 cycles/1 machine cycle
　　- Instruction level compatible with Intel 80C52 64K Bytes on-chip FLASH ROM
　　- ISP by serial interface
　　- IAP and virtual EEPROM for data (2KByte)
　　- Endurance : Typ. 50,000 write/erase cycles.
　　Min. 10,000 write/erase cycles. 16 KBytes on-chip RAM
　　- 256bytes IRAM
　　- 16,384 bytes AUXRAM (Accessed with MOVX) Max. Programmable 32 programmable I/O Pins
　　- Open-drain Intel compatible ports : P0
　　- Quasi-bidirectional Intel compatible ports : P1 ~ P3
　　- Pull-up type ports : P0 ~ P3
　　- Input/Output and pull-up control  : P0 ~ P3
　　- TTL and CMOS compatible logic levels : P0 ~ P3
　　- All ports are initialized during power-on reset. EMI reduction mode : Inhibit ALE 27-bit Programmable Watchdog Timer 10-bit 32-channel ADC Three 16-bit Timer / Counters  Two Full-Duplex UART
　　- Automatic address recognition Two Programmable Counter Arrays
　　- 8-bit / 16-bit dynamic PWM (12 channels).
　　- 16-bit Compare/Capture counter (12channels).
　　- High Speed Output (12 channels). 16 interrupt sources
　　- Timer0/1/2, UART0/1, PCA0/1, WDT, ADC, I2C and 6 External
　　- Four / Two-level interrupt priority Wake-up from Power-Down mode
　　- On-chip Power-On-Reset
　　- External reset
　　- External interrupt 0/1/2/3/4/5
　　- Watchdog Timer Reset Reset scheme
　　- On-chip Power-On-Reset
　　- External reset
　　- Low voltage detector reset
　　- Watchdog Timer Reset if enabled Internal Delay for power stabilization
　　- MCU starts after 50ms from power-up  On-chip PLL
　　- VCO operating frequency : 70MHz ~ 130MHz