单片机解密M30620FCUFP

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　　M30620FCUFP芯片概述：
　　Wait Mode
　　In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. However, if the PM22 bit of PM2 register is “1” (On-chip Oscillator clock for the watchdog timer count source), the watchdog timer remains active. Because the main clock, and On-chip Oscillator clock are on, the peripheral s using these clocks keep operating.
　　-Peripheral Clock Stop
　　If the CM02 bit is “1” (peripheral clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,AT89芯片解密,f8SIO, and f32SIO clocks are turned off when in wait mode, with the power consumption reduced that Much.
　　- Entering Wait Mode
　　The microcomputer is placed into wait mode by executing the WAIT instruction.
　　- Pin Status During Wait Mode
　　Table 1.7.3 lists pin status during wait mode
　　- Exiting Wait Mode
　　The microcomputer is moved out of wait mode by a hardware reset or peripheral interrupt.If the microcomputer is to be moved out of exit wait mode by a hardware reset, set the peripheral interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before executing the WAIT instruction.
　　The peripheral interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral clocks not turned off during wait mode), all peripheral interrupts can be used to exit wait
　　mode. If CM02 bit is “1” (peripheral clocks turned off during wait mode), the peripheral s using the peripheral clocks stop operating, so that only the peripheral s clocked
　　(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not requested).
　　(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal temporary register(Note 1).
　　(3) The I, D and U flags in the FLG register become as follows:
　　The I flag is cleared to “0” (interrupts disabled).
　　The D flag is cleared to “0” (single-step interrupt disabled).
　　The U flag is cleared to “0” (ISP selected).
　　However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is executed.
　　(4) The CPU’s internal temporary register (Note 1) is saved to the stack.
　　(5) The PC is saved to the stack.
　　(6) The interrupt priority level of the accepted interrupt is set in  the IPL.
　　(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
　　After the interrupt sequence is completed, the processor resumes executing instructions from the start address of the interrupt routine.
　　Note: This register cannot be used by user.
　　DMA Request
　　The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS and DSEL3 to DSEL0 bits of DMiSL register (i = 0, 1) on either channel. Table 1.11.4 shows the timing at which the DMAS bit changes state.
　　Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is set to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in a program (it can only be set to “0”).
　　The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore, always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
　　Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the DMAC is enabled.
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